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Si8430/31/35
I S O P R O L O W - POWER TRIPLE-C H A N N E L D I G I TA L ISOLATOR
Features
High-speed operation: DC to 150 Mbps Low propagation delay: <10 ns worst case Wide Operating Supply Voltage: 2.70-5.5V Ultra low power (typical) 5 V Operation: < 1.6 mA per channel at 1 Mbps < 1.9 mA per channel at 10 Mbps < 6 mA per channel at 100 Mbps 2.70 V Operation: < 1.4 mA per channel at 1 Mbps < 1.7 mA per channel at 10 Mbps < 4 mA per channel at 100 Mbps
Pin Assignments
Precise timing (typical): 1.5 ns pulse width distortion 0.5 ns channel-channel skew 2 ns propagation delay skew Up to 2500 VRMS isolation Transient Immunity: 25 kV/s Tri-state outputs with ENABLE control DC correct No start-up initialization required 15 s startup time High temperature operation: 125 C at 150 Mbps Wide body and narrow body SOIC16 packages RoHS-compliant
VDD1 GND1 A1 A2 A3 NC EN1/NC GND1
Wide Body SOIC 16 1 2 15 14 3 4 13 5 12 11 6 7 10 9 8
Top View
VDD2 GND2 B1 B2 B3 NC EN2/NC GND2
Applications

Isolated switch mode supplies Isolated ADC, DAC

Motor control Power factor correction systems
Safety Regulatory Approvals

UL 1577 recognized 2500 VRMS for 1 minute CSA component notice 5A approval IEC 60950, 61010 approved
VDE certification conformity IEC 60747-5-2 (VDE0884 Part 2)
Narrow Body SOIC VDD1 1 16 VDD2 GND1 2 15 GND2 A1 14 B1 3 A2 4 13 B2 A3 5 12 B3 NC 6 11 NC EN1/NC 7 10 EN2/NC GND1 8 9 GND2
Top View
Patents pending
Description
Silicon Lab's family of ultra low power digital isolators are CMOS devices that employ an RF coupler to transmit digital information across an isolation barrier. Very high speed operation at low power levels is achieved. These devices are available in 16-pin wide-body and narrow-body SOIC packages. Two speed grade options (1 and 150 Mbps) are available and achieve worstcase propagation delays of less than 10 ns.
Block Diagram
Si8430/35 Si8431
A1 A2 A3 NC
B1 B2 B3 EN2/NC
A1 A2 A3 EN1
B1 B2 B3 EN2
Rev. 1.2 12/09
Copyright (c) 2009 by Silicon Laboratories
Si8430/31/35
Si8430/31/35
2
Rev. 1.2
Si8430/31/35 TABLE O F CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4. Errata and Design Migration Guidelines (Revision C Only) . . . . . . . . . . . . . . . . . . . . . . 24 4.1. Enable Pin Causes Outputs to Go Low (Revision C Only) . . . . . . . . . . . . . . . . . . . . 24 4.2. Power Supply Bypass Capacitors (Revision C Only) . . . . . . . . . . . . . . . . . . . . . . . .24 4.3. Latch Up Immunity (Revision C Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8. Landing Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10. Landing Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 12. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Rev. 1.2
3
Si8430/31/35
1. Electrical Specifications
Table 1. Electrical Characteristics
(VDD1 = 5 V 10%, VDD2 = 5 V 10%, TA = -40 to 125 C; applies to narrow and wide-body SOIC packages)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Impedance1 Enable Input High Current Enable Input Low Current Si8430Ax, Bx and Si8435Bx VDD1 VDD2 VDD1 VDD2 Si8431Ax, Bx VDD1 VDD2 VDD1 VDD2 Si8430Ax, Bx VDD1 VDD2 Si8431Ax, Bx VDD1 VDD2
Symbol VIH VIL VOH VOL IL ZO IENH IENL
Test Condition
Min 2.0 --
Typ -- -- 4.8 0.2 -- 85 2.0 2.0
Max -- 0.8 -- 0.4 10 -- -- --
Unit V V V V A A A
loh = -4 mA lol = 4 mA
VDD1,VDD2 - 0.4 -- -- --
VENx = VIH VENx = VIL
-- --
DC Supply Current (All inputs 0 V or at Supply) All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC -- -- -- -- -- -- -- -- 1.2 1.9 4.2 1.9 1.7 2.0 3.7 3.0 1.8 2.9 6.3 2.9 2.6 3.0 5.6 4.5
mA
mA
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) -- -- -- -- 2.7 2.2 2.8 2.7 4.1 3.3 4.2 4.1
mA
mA
Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "4. Errata and Design Migration Guidelines (Revision C Only)" on page 24 for more details. 4. Start-up time is the time period from the application of power to valid data at the output.
4
Rev. 1.2
Si8430/31/35
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V 10%, VDD2 = 5 V 10%, TA = -40 to 125 C; applies to narrow and wide-body SOIC packages)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8430Bx, Si8435Bx VDD1 VDD2 Si8431Bx VDD1 VDD2 Si8430Bx, Si8435Bx VDD1 VDD2 Si8431Bx VDD1 VDD2 Timing Characteristics Si843xAx Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew Si843xBx Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 2 See Figure 2 0 -- 3.0 -- -- -- -- -- 6.0 1.5 2.0 0.5 150 6.0 9.5 2.5 3.0 1.8 Mbps ns ns ns ns ns tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 2 See Figure 2 0 -- -- -- -- -- -- -- -- -- -- -- 1.0 250 35 25 40 35 Mbps ns ns ns ns ns -- -- -- -- 2.7 3.0 3.1 3.2 4.1 4.2 4.3 4.5
mA
mA
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) -- -- -- -- 2.9 14.3 7.0 11.0 4.4 17.9 8.8 13.8
mA
mA
Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "4. Errata and Design Migration Guidelines (Revision C Only)" on page 24 for more details. 4. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.2
5
Si8430/31/35
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V 10%, VDD2 = 5 V 10%, TA = -40 to 125 C; applies to narrow and wide-body SOIC packages)
Parameter All Models Output Rise Time Output Fall Time Common Mode Transient Immunity Enable to Data Valid3 Enable to Data Tri-State3 Start-up Time3,4
Symbol
Test Condition CL = 15 pF See Figure 2 CL = 15 pF See Figure 2 VI = VDD or 0 V See Figure 1 See Figure 1
Min
Typ
Max
Unit
tr tf CMTI ten1 ten2 tSU
-- -- -- -- -- --
3.8 2.8 25 5.0 7.0 15
5.0 3.7 -- 8.0 9.2 40
ns ns kV/s ns ns s
Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "4. Errata and Design Migration Guidelines (Revision C Only)" on page 24 for more details. 4. Start-up time is the time period from the application of power to valid data at the output.
ENABLE
OUTPUTS
ten1
ten2
Figure 1. ENABLE Timing Diagram
1.4 V Typical Input
tPLH
90% 1.4 V Typical Output 10% 10% 90%
tPHL
tr
tf
Figure 2. Propagation Delay Timing
6
Rev. 1.2
Si8430/31/35
Table 2. Electrical Characteristics
(VDD1 = 3.3 V 10%, VDD2 = 3.3 V 10%, TA = -40 to 125 C; applies to narrow and wide-body SOIC packages)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Impedance1 Enable Input High Current Enable Input Low Current
Symbol VIH VIL VOH VOL IL ZO IENH IENL
Test Condition
Min 2.0 --
Typ -- -- 3.1 0.2 -- 85 2.0 2.0
Max -- 0.8 -- 0.4 10 -- -- --
Unit V V V V A A A
loh = -4 mA lol = 4 mA
VDD1,VDD2 - 0.4 -- -- --
VENx = VIH VENx = VIL
-- --
DC Supply Current (All inputs 0 V or at supply) Si8430Ax, Bx and Si8435Bx VDD1 VDD2 VDD1 VDD2 Si8431Ax, Bx VDD1 VDD2 VDD1 VDD2 Si8430Ax, Bx VDD1 VDD2 Si8431Ax, Bx VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC -- -- -- -- -- -- -- -- 1.2 1.9 4.2 1.9 1.7 2.0 3.7 3.0 1.8 2.9 6.3 2.9 2.6 3.0 5.6 4.5
mA
mA
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) -- -- -- -- 2.7 2.2 2.8 2.7 4.1 3.3 4.2 4.1
mA
mA
Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "4. Errata and Design Migration Guidelines (Revision C Only)" on page 24 for more details. 4. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.2
7
Si8430/31/35
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V 10%, VDD2 = 3.3 V 10%, TA = -40 to 125 C; applies to narrow and wide-body SOIC packages)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8430Bx, Si8435Bx VDD1 VDD2 Si8431Bx VDD1 VDD2 Si8430Bx, Si8435Bx VDD1 VDD2 Si8431Bx VDD1 VDD2 Timing Characteristics Si843xAx Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 2 See Figure 2 0 -- -- -- -- -- -- -- -- -- -- -- 1.0 250 35 25 40 35 Mbps ns ns ns ns ns -- -- -- -- 2.7 3.0 3.1 3.2 4.1 4.2 4.3 4.5
mA
mA
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) -- -- -- -- 2.8 10.1 5.5 8.0 4.2 12.6 6.9 10.0
mA
mA
Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "4. Errata and Design Migration Guidelines (Revision C Only)" on page 24 for more details. 4. Start-up time is the time period from the application of power to valid data at the output.
8
Rev. 1.2
Si8430/31/35
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V 10%, VDD2 = 3.3 V 10%, TA = -40 to 125 C; applies to narrow and wide-body SOIC packages)
Parameter Si843xBx Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew All Models Output Rise Time Output Fall Time Common Mode Transient Immunity Enable to Data Valid3 Enable to Data Tri-State3 Start-up Time3,4
Symbol
Test Condition
Min
Typ
Max
Unit
0 -- tPHL, tPLH PWD tPSK(P-P) tPSK CL = 15 pF See Figure 2 CL = 15 pF See Figure 2 VI = VDD or 0 V See Figure 1 See Figure 1 See Figure 2 See Figure 2 3.0 -- -- --
-- -- 6.0 1.5 2.0 0.5
150 6.0 9.5 2.5 3.0 1.8
Mbps ns ns ns ns ns
tr tf CMTI ten1 ten2 tSU
-- -- -- -- -- --
4.3 3.0 25 5.0 7.0 15
6.1 4.3 -- 8.0 9.2 40
ns ns kV/s ns ns s
Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "4. Errata and Design Migration Guidelines (Revision C Only)" on page 24 for more details. 4. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.2
9
Si8430/31/35
Table 3. Electrical Characteristics1
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = -40 to 125 C; applies to narrow and wide-body SOIC packages)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Impedance2 Enable Input High Current Enable Input Low Current
Symbol VIH VIL VOH VOL IL ZO IENH IENL
Test Condition
Min 2.0 --
Typ -- -- 2.3 0.2 -- 85 2.0 2.0
Max -- 0.8 -- 0.4 10 -- -- --
Unit V V V V A A A
loh = -4 mA lol = 4 mA
VDD1,VDD2 - 0.4 -- -- --
VENx = VIH VENx = VIL
-- --
DC Supply Current (All inputs 0 V or at supply) Si8430Ax, Bx and Si8435Bx VDD1 VDD2 VDD1 VDD2 Si8431Ax, Bx VDD1 VDD2 VDD1 VDD2 Si8430Ax, Bx VDD1 VDD2 Si8431Ax, Bx VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC -- -- -- -- -- -- -- -- 1.2 1.9 4.2 1.9 1.7 2.0 3.7 3.0 1.8 2.9 6.3 2.9 2.6 3.0 5.6 4.5
mA
mA
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) -- -- -- -- 2.7 2.2 2.8 2.7 4.1 3.3 4.2 4.1
mA
mA
Notes: 1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is constrained to TA = 0 to 85 C. 2. The nominal output impedance of an isolator driver channel is approximately 85 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. See "4. Errata and Design Migration Guidelines (Revision C Only)" on page 24 for more details. 5. Start-up time is the time period from the application of power to valid data at the output.
10
Rev. 1.2
Si8430/31/35
Table 3. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = -40 to 125 C; applies to narrow and wide-body SOIC packages)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8430Bx, Si8435Bx VDD1 VDD2 Si8431Bx VDD1 VDD2 Si8430Bx, Si8435Bx VDD1 VDD2 Si8431Bx VDD1 VDD2 Timing Characteristics Si843xAx Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew3 Channel-Channel Skew tPHL, tPLH PWD tPSK(P-P) tPSK See Figure 2 See Figure 2 0 -- -- -- -- -- -- -- -- -- -- -- 1.0 250 35 25 40 35 Mbps ns ns ns ns ns -- -- -- -- 2.7 3.0 3.1 3.2 4.1 4.2 4.3 4.5
mA
mA
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) -- -- -- -- 2.8 8.0 4.7 6.7 4.2 10 5.9 8.4
mA
mA
Notes: 1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is constrained to TA = 0 to 85 C. 2. The nominal output impedance of an isolator driver channel is approximately 85 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. See "4. Errata and Design Migration Guidelines (Revision C Only)" on page 24 for more details. 5. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.2
11
Si8430/31/35
Table 3. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = -40 to 125 C; applies to narrow and wide-body SOIC packages)
Parameter Si843xBx Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew3 Channel-Channel Skew All Models Output Rise Time Output Fall Time Common Mode Transient Immunity Enable to Data Valid4 Enable to Data Tri-State4 Start-up Time4,5
Symbol
Test Condition
Min
Typ
Max
Unit
0 -- tPHL, tPLH PWD tPSK(P-P) tPSK CL = 15 pF See Figure 2 CL = 15 pF See Figure 2 VI = VDD or 0 V See Figure 1 See Figure 1 See Figure 2 See Figure 2 3.0 -- -- --
-- -- 6.0 1.5 2.0 0.5
150 6.0 9.5 2.5 3.0 1.8
Mbps ns ns ns ns ns
tr tf CMTI ten1 ten2 tSU
-- -- -- -- -- --
4.8 3.2 25 5.0 7.0 15
6.5 4.6 -- 8.0 9.2 40
ns ns kV/s ns ns s
Notes: 1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is constrained to TA = 0 to 85 C. 2. The nominal output impedance of an isolator driver channel is approximately 85 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. See "4. Errata and Design Migration Guidelines (Revision C Only)" on page 24 for more details. 5. Start-up time is the time period from the application of power to valid data at the output.
12
Rev. 1.2
Si8430/31/35
Table 4. Absolute Maximum Ratings1
Parameter Storage Temperature2 Operating Temperature Supply Voltage (Revision C)3 Supply Voltage (Revision Input Voltage Output Voltage Output Current Drive Channel Lead Solder Temperature (10 s) Maximum Isolation Voltage (1 s) D)3 Symbol TSTG TA VDD1, VDD2 VDD1, VDD2 VI VO IO Min -65 -40 -0.5 -0.5 -0.5 -0.5 -- -- -- Typ -- -- -- -- -- -- -- -- -- Max 150 125 5.75 6.0 VDD + 0.5 VDD + 0.5 10 260 3600 Unit C C V V V V mA C VRMS
Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet. 2. VDE certifies storage temperature from -40 to 150 C. 3. See "6. Ordering Guide" on page 26 for more information.
Table 5. Recommended Operating Conditions
Parameter Ambient Operating Temperature* Supply Voltage Symbol TA VDD1 VDD2 Test Condition 150 Mbps, 15 pF, 5 V Min -40 2.70 2.70 Typ 25 -- -- Max 125* 5.5 5.5 Unit C V V
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply voltage.
Table 6. Regulatory Information*
CSA The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873. VDE The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001. UL The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455.
*Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec. For more information, see "6. Ordering Guide" on page 26.
Rev. 1.2
13
Si8430/31/35
Table 7. Insulation and Safety-Related Specifications
Value Parameter Nominal Air Gap (Clearance)1 Nominal External Tracking (Creepage)1 Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Resistance (Input-Output)2 Capacitance (Input-Output)2 Input Capacitance3 CTI RIO CIO CI f = 1 MHz DIN IEC 60112/VDE 0303 Part 1 Symbol L(IO1) L(IO2) Test Condition WB NB SOIC-16 SOIC-16 8.0 8.0 0.008 >175 1012 2.0 4.0 4.9 4.01 0.008 >175 1012 2.0 4.0 Unit mm mm mm V pF pF
Notes: 1. The values in this table correspond to the nominal creepage and clearance values as detailed in "7. Package Outline: 16-Pin Wide Body SOIC" and "9. Package Outline: 16-Pin Narrow Body SOIC". VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB SOIC-16 package and 8.5 mm minimum for the WB SOIC-16 package. UL does not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-16 package and 7.6 mm minimum for the WB SOIC-16 package. 2. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1-8 are shorted together to form the first terminal and pins 9-16 are shorted together to form the second terminal. The parameters are then measured between these two terminals. 3. Measured from input pin to ground.
Table 8. IEC 60664-1 (VDE 0884 Part 2) Ratings
Parameter Basic isolation group Test Conditions Material Group Rated Mains Voltages < 150 VRMS Installation Classification Rated Mains Voltages < 300 VRMS Rated Mains Voltages < 400 VRMS Specification IIIa I-IV I-III I-II
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Rev. 1.2
Si8430/31/35
Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxB*
Parameter Maximum Working Insulation Voltage Symbol VIORM Method a After Environmental Tests Subgroup 1 (VIORM x 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC) Input to Output Test Voltage VPR Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) After Input and/or Safety Test Subgroup 2/3 (VIORM x 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC) Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) Pollution Degree (DIN VDE 0110, Table 1) Insulation Resistance at TS, VIO = 500 V RS VTR Test Condition Characteristic 560 Unit Vpeak
896
1050
Vpeak
672
4000 2 >109
Vpeak
*Note: This isolator is suitable for basic electrical isolation within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of 40/125/21.
Table 10. IEC Safety Limiting Values1
Max Parameter Case Temperature Safety input, output, or supply current Device Power Dissipation2 Symbol TS IS PD JA = 100 C/W (WB SOIC-16), 105 C/W (NB SOIC-16), VI = 5.5 V, TJ = 150 C, TA = 25 C Test Condition Min Typ -- -- -- -- -- -- WB SOIC-16 150 220 275 NB SOIC-16 150 210 275 Unit C mA mW
Notes: 1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 3. 2. The Si843x is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 C, CL = 15 pF, input a 150 Mbps 50% duty cycle square wave.
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Table 11. Thermal Characteristics
Typ Parameter IC Junction-to-Air Thermal Resistance Symbol Test Condition Min WB NB SOIC-16 SOIC-16 100 105 Max Unit
JA
--
--
C/W
500 Safety-Limiting Current (mA)
450
400 300
VDD1, VDD2 = 2.70 V 370 VDD1, VDD2 = 3.6 V 220
200 100 0 0
VDD1, VDD2 = 5.5 V
50
100 Temperature (C)
150
200
Figure 3. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2
500 Safety-Limiting Current (mA)
430
400
360
VDD1, VDD2 = 2.70 V
300
210
VDD1, VDD2 = 3.6 V
200
VDD1, VDD2 = 5.5 V
100 0 0 50 100 Temperature (C) 150 200
Figure 4. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2
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Table 12. Si84xx Logic Operation Table
VI Input1,2 H L X X X EN Input1,2,3,4 H or NC H or NC L H or NC L VDDI State1,5,6 P P P UP UP VDDO VO Output1,2 State1,5,6 P P P P P H Enabled, normal operation. L Hi-Z or L7 L Hi-Z or L7 Disabled. Upon transition of VDDI from unpowered to powered, VO returns to the same state as VI in less than 1 s. Disabled. Comments
X
X
P
UP
Upon transition of VDDO from unpowered to powered, VO returns to the same state as VI Undetermined within 1 s, if EN is in either the H or NC state. Upon transition of VDDO from unpowered to powered, VO returns to Hi-Z with 1 s if EN is L.
Notes: 1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN is the enable control input located on the same output side. 2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance. 3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si84xx is operating in noisy environments. 4. No Connect (NC) replaces EN1 on Si8430/35. No Connect replaces EN2 on the Si8435. No Connects are not internally connected and can be left floating, tied to VDD, or tied to GND. 5. "Powered" state (P) is defined as 2.70 V < VDD < 5.5 V. 6. "Unpowered" state (UP) is defined as VDD = 0 V. 7. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled (EN = 0) in Revision C. Revision D outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See "4. Errata and Design Migration Guidelines (Revision C Only)" on page 24 for more details.
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Table 13. Enable Input Truth Table1
P/N Si8430 EN11,2 EN21,2 -- -- Si8431 H L X X Si8435 -- H L X X H L -- Operation Outputs B1, B2, B3 are enabled and follow input state. Outputs B1, B2, B3 are disabled and Logic Low or in high impedance state.3 Output A3 enabled and follows input state. Output A3 disabled and Logic Low or in high impedance state.3 Outputs B1, B2 are enabled and follow input state. Outputs B1, B2 are disabled and Logic Low or in high impedance state.3 Outputs B1, B2, B3 are enabled and follow input state.
Notes: 1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. These inputs are internally pulled-up to local VDD by a 3 A current source allowing them to be connected to an external logic level (high or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If EN1, EN2 are unused, it is recommended they be connected to an external logic level, especially if the Si84xx is operating in a noisy environment. 2. X = not applicable; H = Logic High; L = Logic Low. 3. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled (EN = 0) in Revision C. Revision D outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See "4. Errata and Design Migration Guidelines (Revision C Only)" on page 24 for more details.
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2. Typical Performance Characteristics
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to Tables 1, 2, and 3 for actual specification limits.
30 25 Current (mA) 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate (Mbps)
30 25 Current (mA)
5V 3.3V 2.70V
20 15 10 5 0 0
5V 3.3V 2.70V
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate (Mbps)
Figure 5. Si8430/35 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation
Figure 8. Si8430/35 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation (15 pF Load)
30 25 5V 3.3V
30 25 Current (mA) 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate (Mbps) 2.70V 5V 3.3V
Current (mA)
20 15 10 5 0 0
2.70V
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate (Mbps)
Figure 6. Si8431 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation
Figure 9. Si8431 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation (15 pF Load)
10 9 Delay (ns) 8 7 Rising Edge 6 5 -40 -20 0 20 40 60 80 100 120 Temperature (Degrees C) Falling Edge
Figure 7. Propagation Delay vs. Temperature
Rev. 1.2
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3. Application Information
3.1. Theory of Operation
The operation of an Si843x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single Si843x channel is shown in Figure 10.
Transmitter
RF OSCILLATOR
Receiver
A
MODULATOR
SemiconductorBased Isolation Barrier
DEMODULATOR
B
Figure 10. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See Figure 11 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 11. Modulation Scheme
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3.2. Eye Diagram
Figure 12 illustrates an eye-diagram taken on an Si8430. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8430 were captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width distortion and 250 ps peak jitter were exhibited.
Figure 12. Eye Diagram
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3.3. Layout Recommendations
Dielectric isolation is a set of specifications produced by the safety regulatory agencies from around the world that describes the physical construction of electrical equipment that derives power from a high-voltage power system such as 100-240 VAC systems or industrial power systems. The dielectric test (or HIPOT test) given in the safety specifications places a very high voltage between the input power pins of a product and the user circuits and the user touchable surfaces of the product. For the IEC relating to products deriving their power from the 100-240 VAC power grids, the minimum test voltage is 2500 VAC (or 3750 VDC--the peak equivalent voltage). There are two terms described in the safety specifications: Creepage--the distance along the insulating surface an arc may travel. Clearance--the distance through the shortest path through air that an arc may travel. Figure 13 illustrates the accepted method of providing the proper creepage distance along the surface. For a 120 VAC application, this distance is 3.2 mm, and the narrow-body SOIC package can be used. For a 220-240 VAC application, this distance is 6.4 mm, and a wide-body SOIC package must be used. There must be no copper traces within this 3.2 or 6.4 mm exclusion area, and the surface should have a conformal coating, such as solder resist. The digital isolator chip must straddle this exclusion area.
IEC Specified Creepage Distance
Figure 13. Creepage Distance
3.3.1. Supply Bypass The Si843x requires a 1 F bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be placed as close as possible to the package. See "4. Errata and Design Migration Guidelines (Revision C Only)" on page 24 for more details. 3.3.2. Pin Connections For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin 15 must also be connected to external ground. No connect pins are not internally connected. They can be left floating, tied to VDD, or tied to GND. 3.3.3. Output Pin Termination The nominal output impedance of an isolator driver channel is approximately 85 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
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3.3.4. RF Radiated Emissions The Si843x family uses a RF carrier frequency of approximately 700 MHz. This results in a small amount of radiated emissions at this frequency and its harmonics. The radiation is not from the IC but, rather, is due to a small amount of RF energy driving the isolated ground planes, which can act as a dipole antenna. The unshielded Si8430 evaluation board passes FCC Class B (Part 15) requirements. Table 14 shows measured emissions compared to FCC requirements. Note that the data reflects worst-case conditions where all inputs are tied to logic 1 and the RF transmitters are fully active. Radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the PCB is a less efficient antenna.
Table 14. Radiated Emissions
Frequency Measured (MHz) (dBV/m) 712 1424 2136 2848 4272 4984 5696 29 39 42 43 44 44 44 FCC Spec (dBV/m) 37 54 54 54 54 54 54 Compared to Spec (dB) -8 -15 -12 -11 -10 -10 -10
3.3.5. RF, Magnetic, and Common Mode Transient Immunity The Si84xx families have very high common mode transient immunity while transmitting data. This is typically measured by applying a square pulse with very fast rise/fall times between the isolated grounds. Measurements show no failures at 25 kV/s (typical). During a high surge event, the output may glitch low for up to 20-30 ns, but the output corrects immediately after the surge event. The Si84xx families pass the industrial requirements of CISPR24 for RF immunity of 10 V/m using an unshielded evaluation board. As shown in Figure 14, the isolated ground planes form a parasitic dipole antenna. The PCB should be laid-out to not act as an efficient antenna for the RF frequency of interest. RF susceptibility is also significantly reduced when the end system is housed in a metal enclosure, or otherwise shielded. The Si843x digital isolator can be used in close proximity to large motors and various other magnetic-field producing equipment. In theory, data transmission errors can occur if the magnetic field is too large and the field is too close to the isolator. However, in actual use, the Si84xx devices provide extremely high immunity to external magnetic fields and have been independently evaluated to withstand magnetic fields of at least 1000 A/m according to the IEC 61000-4-8 and IEC 61000-4-9 specifications.
GND1
Isolator
GND2
Dipole Antenna
Figure 14. Dipole Antenna
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4. Errata and Design Migration Guidelines (Revision C Only)
The following errata apply to Revision C devices only. See "6. Ordering Guide" on page 26 for more details. No errata exist for Revision D devices.
4.1. Enable Pin Causes Outputs to Go Low (Revision C Only)
When using the enable pin (EN1, EN2) function on the ISOpro 3-channel (Si8430/1), the corresponding output pin states (pin = An, Bn, where n can be 1...3) are driven to a logic low (to ground) when the enable pin is disabled (EN1 or EN2 = 0). This functionality is different from the legacy 3-channel (Si8430/1) isolators. On those devices, the isolator outputs go into a high-impedance state (Hi-Z) when the enable pin is disabled (EN1 = 0 or EN2 = 0). 4.1.1. Resolution The enable pin functionality causing the outputs to go low is supported in production for Revision C of the ISOpro devices. Revision D corrects the enable pin functionality (i.e., the outputs will go into the high-impedance state to match the legacy isolator products). Refer to the Ordering Guide sections of the data sheet(s) for current ordering information.
4.2. Power Supply Bypass Capacitors (Revision C Only)
When using the ISOpro isolators with power supplies > 4.5 V, sufficient VDD bypass capacitors must be present on both the VDD1 and VDD2 pins to ensure the VDD rise time is less than 0.5 V/s (which is > 9 s for a > 4.5 V supply). Although rise time is power supply dependent, > 1 F capacitors are required on both power supply pins (VDD1, VDD2) of the isolator device. 4.2.1. Resolution This issue has been corrected with Revision D of the device. Refer to "6. Ordering Guide" for current ordering information.
4.3. Latch Up Immunity (Revision C Only)
ISOpro latch up immunity generally exceeds 200 mA per pin. Exceptions: Certain pins provide < 100 mA of latchup immunity. To increase latch-up immunity on these pins, 100 of equivalent resistance must be included in series with all of the pins listed in Table 15. The 100 equivalent resistance can be comprised of the source driver's output resistance and a series termination resistor. The Si8431 is not affected when using power supply voltages (VDD1 and VDD2) < 3.5 V. 4.3.1. Resolution This issue has been corrected with Revision D of the device. Refer to "6. Ordering Guide" for current ordering information.
Table 15. Affected Ordering Part Numbers (Revision C Only)
Affected Ordering Part Numbers* Device Revision C Pin# 5 SI8430SV-C-IS/IS1, SI8431SV-C-IS/IS1 10 14 SI8435SV-C-IS/IS1 C 5 14 Name A3 EN2 B1 A3 B1 Pin Type Input or Output Input Output Input Output
*Note: "SV" = Speed Grade/Isolation Rating (AA, AB, BA, BB).
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5. Pin Descriptions
VDD1 GND1 A1 A2 A3 NC EN1/NC GND1
1 2 3 4 5 6 7 8
Top View
16 15 14 13 12 11 10 9
VDD2 GND2 B1 B2 B3 NC EN2/NC GND2
Name VDD1 GND1 A1 A2 A3 NC EN1/NC2 GND1 GND2 EN2/NC NC B3 B2 B1 GND2 VDD2
2
SOIC-16 Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Type Supply Ground Digital Input Digital Input Digital I/O NA Digital Input Ground Ground Digital Input NA Digital I/O Digital Output Digital Output Ground Supply
Description1 Side 1 power supply. Side 1 ground. Side 1 digital input. Side 1 digital input. Side 1 digital input or output. No Connect. Side 1 active high enable. NC on Si8430/35 Side 1 ground. Side 2 ground. Side 2 active high enable. NC on Si8435. No Connect. Side 2 digital input or output. Side 2 digital output. Side 2 digital output. Side 2 ground. Side 2 power supply.
Notes: 1. For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin 15 must also be connected to external ground. 2. No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
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6. Ordering Guide
Revision D devices are recommended for all new designs.
Si84XYSV-R-TPn
Isolator Product Data channel count Reverse channel count Max Data Rate (A=1Mbps,B=150Mbps) Insulation Rating (A=1kV, B=2.5kV) Product Revision Temp Range (I=-40 to +125C) Package Type (S=SOIC) Package Extension (1=Narrow Body- 16 pin)
Figure 15. Ordering Part Number (OPN) Convention Table 16. Ordering Guide for Valid OPNs1
Ordering Part Number (OPN) Si8430AB-D-IS Si8430BB-D-IS Si8431AB-D-IS Si8431BB-D-IS Si8435BB-D-IS Si8430AB-D-IS1 Si8430BB-D-IS1 Si8431AB-D-IS1 Si8431BB-D-IS1 Si8435BB-D-IS1 Number of Number of Inputs VDD1 Inputs VDD2 Side Side 3 3 2 2 3 3 3 2 2 3 0 0 1 1 0 0 0 1 1 0 Maximum Data Rate (Mbps) 1 150 1 150 150 1 150 1 150 150 2.5 kVrms -40 to 125 C NB SOIC-161 2.5 kVrms -40 to 125 C WB SOIC-161 Isolation Rating Temp Range Package Type
Notes: 1. All packages are RoHS-compliant. Moisture sensitivity level is MSL3 for wide-body SOIC-16 packages and MSL2A for narrow-body SOIC-16 packages with peak reflow temperatures of 260 C according to the JEDEC industry standard classifications and peak solder temperatures. 2. Revision C devices are supported for existing designs, but Revision D is recommended for all new designs.
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Table 16. Ordering Guide for Valid OPNs1 (Continued)
Ordering Part Number (OPN) Revision C Devices2 Si8430AB-C-IS2 Si8430BB-C-IS2 SI8431AB-C-IS2 Si8431BB-C-IS2 Si8435BB-C-IS2 Si8430AB-C-IS12 Si8430BB-C-IS12 SI8431AB-C-IS1
2
Number of Number of Inputs VDD1 Inputs VDD2 Side Side
Maximum Data Rate (Mbps)
Isolation Rating
Temp Range
Package Type
3 3 2 2 3 3 3 2 2 3
0 0 1 1 0 0 0 1 1 0
1 150 1 150 150 1 150 1 150 150 2.5 kVrms -40 to 125 C NB SOIC-161 2.5 kVrms -40 to 125 C WB SOIC-161
Si8431BB-C-IS12 Si8435BB-C-IS12
Notes: 1. All packages are RoHS-compliant. Moisture sensitivity level is MSL3 for wide-body SOIC-16 packages and MSL2A for narrow-body SOIC-16 packages with peak reflow temperatures of 260 C according to the JEDEC industry standard classifications and peak solder temperatures. 2. Revision C devices are supported for existing designs, but Revision D is recommended for all new designs.
Rev. 1.2
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7. Package Outline: 16-Pin Wide Body SOIC
Figure 16 illustrates the package details for the Triple-Channel Digital Isolator. Table 17 lists the values for the dimensions shown in the illustration.
Figure 16. 16-Pin Wide Body SOIC Table 17. Package Diagram Dimensions
Millimeters Symbol A A1 D E E1 b c e h L 0.25 0.4 0 0.31 0.20 1.27 BSC 0.75 1.27 7 Min -- 0.1 10.3 BSC 10.3 BSC 7.5 BSC 0.51 0.33 Max 2.65 0.3
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8. Landing Pattern: 16-Pin Wide-Body SOIC
Figure 17 illustrates the recommended landing pattern details for the Si843x in a 16-pin wide-body SOIC. Table 18 lists the values for the dimensions shown in the illustration.
Figure 17. 16-Pin SOIC Land Pattern Table 18. 16-Pin Wide Body SOIC Landing Pattern Dimensions
Dimension C1 E X1 Y1 Feature Pad Column Spacing Pad Row Pitch Pad Width Pad Length (mm) 9.40 1.27 0.60 1.90
Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
Rev. 1.2
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Si8430/31/35
9. Package Outline: 16-Pin Narrow Body SOIC
Figure 18 illustrates the package details for the Si84xx in a 16-pin narrow-body SOIC (SO-16). Table 19 lists the values for the dimensions shown in the illustration.
Figure 18. 16-pin Small Outline Integrated Circuit (SOIC) Package Table 19. Package Diagram Dimensions
Dimension A A1 A2 b c D E E1 e L L2 0.40 0.25 BSC Min -- 0.10 1.25 0.31 0.17 9.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 1.27 Max 1.75 0.25 -- 0.51 0.25
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Table 19. Package Diagram Dimensions (Continued)
h aaa bbb ccc ddd 0.25 0 0.10 0.20 0.10 0.25 0.50 8
Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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10. Landing Pattern: 16-Pin Narrow Body SOIC
Figure 19 illustrates the recommended landing pattern details for the Si843x in a 16-pin narrow-body SOIC. Table 20 lists the values for the dimensions shown in the illustration.
Figure 19. 16-Pin Narrow Body SOIC PCB Landing Pattern Table 20. 16-Pin Narrow Body SOIC Landing Pattern Dimensions
Dimension C1 E X1 Y1 Feature Pad Column Spacing Pad Row Pitch Pad Width Pad Length (mm) 5.40 1.27 0.60 1.55
Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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11. Top Marking: 16-Pin Wide Body SOIC
Si84XYSV YYWWTTTTTT e3 TW
Figure 20. Si8430/31/35 Top Marking Table 21. Top Marking Explanation
Si84 = Isolator product series XY = Channel Configuration Base Part Number X = # of data channels (3, 2, 1) Ordering Options Y = # of reverse channels (1, 0)* S = Speed Grade (See Ordering Guide for more A = 1 Mbps; B = 150 Mbps information). V = Insulation rating A = 1 kV; B = 2.5 kV YY = Year WW = Workweek TTTTTT = Mfg Code Circle = 1.5 mm Diameter (Center-Justified) Country of Origin ISO Code Abbreviation Assigned by Assembly House Manufacturing Code from Assembly House "e3" Pb-Free Symbol TW = Taiwan
Line 1 Marking:
Line 2 Marking:
Line 3 Marking:
*Note: Si8435 has 0 reverse channels.
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12. Top Marking: 16-Pin Narrow Body SOIC
e3
Si84XYSV YYWWTTTTTT
Figure 21. 16-Pin Narrow Body SOIC Top Marking Table 22. 16-Pin Narrow Body SOIC Top Marking Table
Line 1 Marking: Base Part Number Ordering Options (See Ordering Guide for more information). Si84 = Isolator product series XY = Channel Configuration X = # of data channels (3, 2, 1) Y = # of reverse channels (1, 0)* S = Speed Grade A = 1 Mbps; B = 150 Mbps V = Insulation rating A = 1 kV; B = 2.5 kV "e3" Pb-Free Symbol Assigned by the Assembly House. Corresponds to the year and work week of the mold date. Manufacturing Code from Assembly Purchase Order form. "e3" Pb-Free Symbol.
Line 2 Marking:
Circle = 1.2 mm Diameter YY = Year WW = Work Week TTTTTT = Mfg code Circle = 1.2 mm diameter
*Note: Si8435 has 0 reverse channels.
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DOCUMENT CHANGE LIST
Revision 0.32 to Revision 0.33
Revision 1.0 to Revision 1.1
Updated Tables 1, 2, and 3.
Updated
notes in tables to reflect output impedance of rise and fall time specifications. CMTI value.
Rev 0.33 is the first revision of this document that applies to the new series of ultra low power isolators featuring pinout and functional compatibility with previous isolator products. Updated "1. Electrical Specifications". Updated "6. Ordering Guide". Added "11. Top Marking: 16-Pin Wide Body SOIC".
85 .
Updated Updated
Revision 1.1 to Revision 1.2
Updated document throughout to include MSL improvements to MSL2A. Updated "6. Ordering Guide" on page 26.
Updated
Revision 0.33 to Revision 0.34
Updated all specs to reflect latest silicon.
Note 1 in ordering guide table to reflect improvement and compliance to MSL2A moisture sensitivity level.
Revision 0.34 to Revision 0.35
Updated all specs to reflect latest silicon. Added "4. Errata and Design Migration Guidelines (Revision C Only)" on page 24. Added "12. Top Marking: 16-Pin Narrow Body SOIC" on page 34.
Revision 0.35 to Revision 1.0
Updated document to reflect availability of Revision D silicon. Updated Tables 1,2, and 3.
Updated
all supply currents and channel-channel skew. absolute maximum supply voltage. clearance and creepage dimensions. Note 7. Note 3.

Updated Table 4.
Updated
Updated Table 7.
Updated
Updated Table 12.
Updated
Updated Table 13.
Updated
Updated "4. Errata and Design Migration Guidelines (Revision C Only)" on page 24. Updated "6. Ordering Guide" on page 26.
Rev. 1.2
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CONTACT INFORMATION
Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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